Keysight Technologies Provides 5G Service Quality Monitoring for Mobile Operators

Beijing, China, February 5, 2021 – Keysight Technologies (NYSE: KEYS) announced MobileStack, a new user session monitoring capability in the Vision X high-performance Network Packet Broker (NPB) for 4G and 5G The core network provides scalable and user-identifiable network visualization services, thereby improving service quality and reducing costs. Keysight Technologies is a leading technology company dedicated to helping enterprises, service providers and government customers accelerate innovation and create a secure, connected world.

Mobile data volumes continue to explode as more and more users use 5G. According to data analysis by Ericsson, total global mobile data traffic is expected to reach around 51 exabytes (EB) per month by the end of 2020, and will grow by about 4.5 times to 226 EB per month by 2026. The telecom industry expects 5G to have a greater impact on mobile traffic than previous generations of technology. Therefore, 5G requires more monitoring of users and traffic to ensure quality of service (QoS).

“Mobile network operators are already dealing with an explosion of data, but as 5G enters our lives, data growth will drive mobile infrastructure (especially is monitoring capabilities) pushing the limits. Mobile operators urgently need a solution that allows them to strategically monitor subscribers and network traffic without increasing costs. MobileStack provides mobile network operators with the network visibility and The ability to control allows them to provide users with higher quality services while reducing costs and gaining a competitive advantage.”

MobileStack on Keysight Vision X provides mobile network operators with the following key advantages:

Provides zero-packet-loss visibility of mobile user activity, enabling monitoring probes for accurate results.

· Reduced monitoring costs, thereby increasing profit margins per user.

Ability to expand surveillance in existing 4G networks and smoothly transition to 5G to handle expected 5G traffic growth.

· Can effectively manage user traffic and effectively evaluate service quality while reducing monitoring probe load.

About Keysight

Keysight Technologies (NYSE: KEYS) is a leading technology company dedicated to helping enterprises, service providers and government customers accelerate innovation and create a secure, connected world. From design simulation, prototyping, production testing to network and cloud optimization, Keysight provides a full range of test and analysis solutions to help customers deeply optimize their networks, so that their Electronic products can be delivered at a lower cost and faster. to market. Our customers span the global communications ecosystem, aerospace and defense, automotive, energy, semiconductor and general electronics end markets. In fiscal 2020, Keysight’s revenue was $4.2 billion.

The Links:   PM30CNA060 2MI50F-050 MY IGBT

TSMC established a Japanese R&D center with half of the Japanese government’s investment

News on June 1, according to Japanese media reports, the Ministry of Economy, Trade and Industry of Japan announced yesterday that it will support TSMC to establish a semiconductor R&D center in Japan, and will invest half of the cost, about 18.5 billion yen (about 1.076 billion yuan), aiming at advanced technology. Semiconductor technology research and development.

More than 20 well-known companies in the industry chain, including Shin-Etsu Chemical and Asahi Kasei, will also participate in the plan.

TSMC responded by saying that it is grateful for Japan’s official support and looks forward to working with Japanese partners to promote the advancement of semiconductor technology.

It is reported that the Ministry of Economy, Trade and Industry of Japan has subsidized TSMC for two projects, one is the research and development of communication infrastructure in the post-5G era, and the other is the development of advanced semiconductor manufacturing technology. Participating companies include Japan’s Sony Semiconductor, Sumitomo, Showa Denko Materials and other companies, as well as institutions such as the Industrial Technology Research Institute and the University of Tokyo.

TSMC has accelerated its global layout in recent years, announced investment plans in the United States, mainland China, Japan and other places, and is negotiating with Europe. It is worth mentioning that TSMC’s Nanjing production expansion plan has caused a lot of controversy on Chinese social media. In the United States, TSMC has joined the American Semiconductor Alliance and will work with American companies such as Intel to fight for up to $50 billion in US semiconductor policy funds.

Source: C114 Communication Network

Author: Nanshan

The Links:   TM25DZ-H G104SN02 V1

Silicon Labs’ New Wireless SoCs Enable Digital Transformation in Every Industry

Silicon Labs announced a new line of secure, proprietary wireless system-on-chip (SoC) products. These SoCs are designed for battery- or energy-harvesting-powered IoT products that are power- and size-constrained, and target applications include Electronic shelf labels (ESL), building security, industrial automation sensors, and custom modules for commercial lighting. Based on Silicon Labs’ Wireless Gecko Series 2 platform, the new EFR32FG22 (FG22) SoCs offer the best combination of security features, 2.4 GHz wireless performance, power efficiency, software tools and protocol stacks to support next-generation ESL and price tag automation products.


According to data from Mordor Intelligence, the global ESL market was valued at over $581 million in 2019 and is expected to reach $1.82 billion by 2025, growing at a compound annual growth rate (CAGR) of over 21% during 2020-2025. ESL technology enables cloud-based applications that enhance retail automation, shopper engagement and data analytics. Most ESL system designs are based on proprietary wireless protocols, and Silicon Labs’ new FG22 SoC provides a leading connectivity solution for this rapidly growing market.

Ross Sabolcik, vice president and general manager of IoT commercial and industrial products at Silicon Labs, said: “IoT developers deploy custom wireless protocols across multiple applications to radically optimize their systems for high performance and low power consumption. We design The launch of the FG22 product family helps customers quickly deliver optimized, cost-effective solutions for demanding applications such as ESL based on our latest Series 2 wireless SoCs.”

The FG22 integrates a 38.4 MHz Arm® Cortex®-M33 core with TrustZone and a high-performance radio with -106.4 dBm receive sensitivity. The SoC provides excellent energy efficiency with ultra-low transmit and receive power (8.2 mA TX, 3.6 mA RX at +6 dBm) and 1.2 µA deep sleep mode power consumption. Additional low-power on-chip features such as RFSense, which enables RF energy to wake the FG22, further extend the lifespan of IoT products with limited battery or energy harvesting options.

Silicon Labs offers an industry-leading combination of security features in all Series 2 products, including the new FG22 SoC.

The Links:   G150XG03 V1 CM150MXUD-24T IGBTS

Two Methods for Amplifier Stability Analysis Using SPICE

When engineers design op amps, they often use SPICE simulation to check the stability of the designed circuit. SPICE simulation is especially common in high-speed amplifier applications, where tiny capacitances and inductances can easily affect circuit stability.


When engineers design op amps, they often use SPICE simulation to check the stability of the designed circuit. SPICE simulation is especially common in high-speed amplifier applications, where tiny capacitances and inductances can easily affect circuit stability.

A typical approach to stability analysis is to insert AC breakpoints in the feedback loop so that the loop gain (Aol × β) response can be measured using AC analysis, which is applicable to almost all SPICE simulators. However, the exact location where the feedback network inserts the breakpoint may have a greater impact on the accuracy of the simulation.

This article will use the OPA607 op amp to illustrate the pros and cons of two of the most common insertion positions engineers use in feedback networks.

Method 1: Break the loop at the output

In this stability analysis method, the feedback loop at the output of the amplifier is disconnected. This is a fairly simple and popular method. Figure 1 shows a typical example of this approach.

Figure 1: The stability simulation circuit breaks the loop at the output.Source of this article: Texas Instruments

Op amps very effectively demonstrate the difference between the two approaches; let’s explore why. In the circuit of Figure 1, the loop is broken using a 1TH Inductor at the output. It is important to use a very large inductor to break the loop, rather than just disconnect it completely, so that the simulation can still calculate the DC operating point for the analysis, but it appears to be an open circuit for the AC simulation. Without the inductor, the simulation may not be able to find the operating point for the simulation, or it will find an inaccurate operating point due to the loop being broken at the output, while the input is connected to the output of the feedback network, from the input source The transfer function to the amplifier output will be equal to the feedback factor (β) multiplied by the amplifier’s open-loop gain (Aol), commonly referred to as the loop gain. Then, to get the phase margin, you can run an AC simulation and evaluate the loop gain phase for amplitudes above 0dB. Figure 2 shows the simulation results for stability from 10MHz to 100MHz, with a phase margin of approximately 82 degrees.

Figure 2: Stability simulation results obtained using method one.

Method 2: Disconnect the loop at the inverting node

Another logical place to disconnect the feedback network out of the output is the inverting input of the amplifier. Figure 3 shows an example circuit for stability simulation similar to Figure 1, but where the loop is broken at the input of the amplifier, not the output.

Figure 3: The stability simulation circuit breaks the loop at the input.

In the circuit of Figure 3, notice the two extra capacitors (Ccm and Cdiff) added to the circuit’s feedback loop. These capacitors represent the common-mode and differential input capacitances of the amplifier, respectively. With method two, they must be added back into the feedback loop as discrete components, because breaking the loop at the input disconnects the Model’s input capacitance from the feedback network, which can significantly affect response accuracy.

Amplifier input capacitance values ​​are listed on most amplifier data sheets. For the OPA607, the common mode capacitance is 5.5pF and the differential capacitance is 11.5pF. The differential capacitor is usually connected to the non-inverting input, but since the non-inverting input is grounded in this example, the Cdiff capacitor is also grounded.

By analyzing the circuit shown in Figure 3, you can see that the transfer function between the input and output labeled “Loop Gain” is actually the same as that of the circuit in Figure 1, where Loop Gain = Aol × β . The inductor also acts to break the AC loop, while also providing the proper DC operating point.

Figure 4 shows the loop gain simulated response of the circuit in Figure 3, with a phase margin of approximately 91 degrees. The attentive reader will quickly notice that this phase margin is nearly 10 degrees higher than that obtained using method one in Figure 2. What is the root cause of the different simulation results? How do you get equivalent results from two simulations?

Figure 4: Stability simulation results obtained using method two.

How can I make the results of the two methods equivalent?

To obtain equivalent results from either method, it is important to understand the differences between the two circuits that may cause the simulated responses to differ. The fundamental difference between the two circuits is how the loading of the amplifier differs between the two approaches. In method two, the amplifier is loaded by the feedback network; any effect this has on the amplifier response will show up in the loop gain simulation. However, method one completely separates the feedback network from the loading of the amplifier output because of the loop break at the output.

This may not be a problem for an amplifier whose response is not affected by the amplifier load, but this assumption cannot always be made. The OPA607 is an example of this phenomenon, as the loading of the amplifier directly affects the response and thus the stability of the circuit.

Fortunately, you can work around the feedback network loading problem of method one by adding a separate load at the output of the amplifier to represent the load that the feedback network typically presents. Figure 5 shows the modified circuit with an equivalent 700 Ω load on the output of the OPA607 to account for the normal loading of the feedback network. In this case, the load is a simple 700 Ω, but a more complex feedback network (such as that of an active filter) requires all components of the feedback network to be included in the equivalent load.

Figure 5: Modified circuit diagram considering output load in Method 1.

Figure 6 shows the new results for the improved circuit using method one, with a measured phase margin of approximately 91 degrees, a difference of 0.14dB from the result from method two. For functional model SPICE simulations, this small difference is within an acceptable margin of error.

Figure 6: Loop gain simulation results obtained using the modified circuit of method one.

Which method should be chosen?

After the above discussion, knowing that you can achieve similar results using either method, which method should you choose for your simulation? The answer really comes down to which method you prefer.

In Method 1, there is no need to figure out the input capacitance of the amplifier, but an additional equivalent load needs to be added to the amplifier output.

Method 2 requires knowledge of the amplifier’s input capacitance, but couples the output to the feedback network. Method two can reduce the complexity of circuits with complex feedback networks, but for circuits with more complex input networks (such as differential amplifiers), it can be confusing how to set it up correctly.

In conclusion, both methods have their advantages and disadvantages. The most important conclusion of this analysis is not to say that one method is better than the other, but to always ensure that the amplifier and feedback network have an equivalent load impedance to the closed-loop circuit wherever the loop is broken.

The Links:   LJ64ZU51 SKIIP23NAB126V1

Power semiconductor cold knowledge: power density of power devices

The development direction of chip technology is to reduce conduction loss and dynamic loss. The development direction of packaging reduces the parasitic inductance, allowing the chip to switch quickly without oscillation; improve the reliability of the packaging process, improve the power cycle and temperature cycle, that is to say, while increasing the junction temperature of the device, it must also ensure the life of the device. Improve heat dissipation and reduce junction-to-case thermal resistance Rthjc.

Ziying Chen, Infineon Industrial semiconductor

Power semiconductors are destined to withstand large power losses, high temperatures and temperature changes. Improving the power density of devices and systems is an important design goal of power semiconductors. We pursue the output current capability per unit chip area all the way, and the realization method is as follows:

1. Reduce conduction loss and dynamic loss
2. Reduce parasitic inductance and give full play to the switching speed of the chip
3. Increase the maximum allowable operating junction temperature
4. Reduce junction-to-case thermal resistance Rthjc

The development direction of chip technology is to reduce conduction loss and dynamic loss. The development direction of packaging reduces the parasitic inductance, allowing the chip to switch quickly without oscillation; improve the reliability of the packaging process, improve the power cycle and temperature cycle, that is to say, while increasing the junction temperature of the device, it must also ensure the life of the device. Improve heat dissipation and reduce junction-to-case thermal resistance Rthjc.

It can be seen in the formula that technological progress has increased Tvj and reduced Rthjc, which allows the device to withstand a greater loss Vce*Ic, which means that the heat generation on the chip is allowed to be greater.

Let’s make an interesting comparison with the Sun’s specific power density.

Infineon’s appearance is the star product:

EconoDUAL™3, FF900R12ME7_B11,
900A 1200V IGBT7.
Power Density of FF900R12ME7_B11

The first working condition:

Solve the power density of the FF900R12ME7_B11 IGBT module at a case temperature of 80 degrees. Transform the above formula:

The allowable power consumption of a 900A 1200V chip is 1549 watts when the case temperature is 80 degrees. If the dynamic switching loss is not considered in the case of DC, Ptot=Vcesat*Ic, since the typical value of the saturation voltage drop is 1.7V, at this time Device collector current (without switching losses) is around 911A.

Since the chip area of ​​900A IGBT is about 6cm², the power density is: 2.6*10⁶W/m². At this time, the chip power density of IGBT7 is one order of magnitude higher than that of a match flame and 9 orders of magnitude higher than that of an electric iron! ! !

The second working condition is short circuit:

The IGBT is connected to the 900V DC bus, and the first type of short-circuit experiment is carried out. The bus voltage is 900V during short-circuit, and within 8us, the short-circuit current can reach more than 3200A, and the instantaneous power is as high as P=900V*3200A=2.88MW!!!

In the same way, it is calculated that the power density of the chip is as high as 4.8*10⁹ W/m², which is 2 orders of magnitude higher than the power density of the solar surface of 5.0*10⁷W/m²! ! !


1. The mass of a match is about 0.065g, and the calorific value of wood is about 1.2×107J/kg. Assuming that the cross-sectional area of ​​the flame is 100mm2, the match will burn out in 15 seconds.

2. The median value of human exercise fever is 200W, and the surface area of ​​the human body is based on Xu Wensheng’s formula: body surface area (m2) = 0.0061 × height (cm) + 0.0128 × weight (kg) – 0.1529

IGBT temperature

In the system design, the working junction temperature of the IGBT is generally 100°C higher than the boiling point of water, the design target is 150°C, and the transient is as high as 175°C.In the cooling water pump of the hydrogen fuel cell, the cooling liquid temperature of the IGBT in the driver may be 95 degrees. Under such harsh working conditions, the driving kilometers and service life of the vehicle must also be met, and the reliability and service life of the IGBT are highly required.

The challenge of high power density

Due to the very high requirements on the operating temperature and power density of power semiconductors in the design of power Electronic systems, it is a great challenge for the design and production of chip technology and packaging technology.

Solder layer

High temperature and large case temperature change will cause the mechanical fatigue of the module solder layer to separate, which will increase the thermal resistance Rthjc from the junction to the case, and then fail.

binding wire

Only after the comparison can we know that the power density of the IGBT chip is so high, now let’s study the design specification and current density of the bonding wire.

There is a less noticeable parameter in the data sheet of the module, the module lead resistance, that is, the resistance value RCC’+EE’ from the terminal to the chip, this resistance value does not seem to be too much loss for small current modules, but this The current density of the bonding wire is as high as 254A/mm², which is much higher than the current density of 6A/mm² of the copper wire in the household power distribution specification. If the lead wire of the 900A module is designed according to the aluminum wire current density of 2.5A/mm, the lead wire of the 900A module needs to be 360mm², which will be an aluminum row with a cross-section of 60*60mm.

The repeated flow of such a high-density current through the bonding wire will cause mechanical stress on the bonding wire, resulting in mechanical damage such as cracking of the bonding wire.

One end of the bonding wire is connected to the metallization layer of the IGBT chip, which is a 3.2um thick AlSiCu material. This connection point is also a weak link that is prone to mechanical fatigue. Large junction temperature changes will cause another failure mechanism. Alignment is off.

Datasheet for the IGC193T120T8RM 200A 1200V chip

Packaging efficiency

The lead resistance of the module, that is, the resistance value RCC’+EE’ from the terminal to the chip, will cause the loss, which is not a small value for medium and high power modules.

EconoDUAL™3 FF900R12ME7 module lead resistance, the resistance value from terminal to chip is 0.8mΩ, the voltage drop is 0.72V at 900A, and the power consumption is as high as 648W.

FF900R12ME7 Current and Lead Loss

If the PrimePACK™ package is selected, its maximum specification is 2400A half bridge, and the lead resistance of such a module is much lower, because the terminal adopts a copper bar structure. FF900R12IE4, the resistance value from the 900A 1200V module terminal to the chip is 0.3mΩ, the voltage drop at 900A is 0.27V, and the power consumption is only 243W, which is only 38% of the EconoDUAL™3 FF900R12ME7.

Therefore, when selecting a device, it is necessary to consider the characteristics of different packages to meet the system requirements.

in conclusion:

From this point of view, the main problem caused by high power density is to cause mechanical fatigue of the device and affect the life of the device. Fortunately, these life mechanisms are known and can be described by power cycles and temperature cycles. The life of the device and system can be designed.

In order to evaluate the life of the device in the system in the application fields of wind power generation, electric vehicle and locomotive traction, etc. with large load changes, it is necessary to further understand the life mechanism and design method of the device. Infineon provides a fee-based service for life simulation.

The Links:   KCB104VG2BA-A21 LQ150X1LW73

Pay attention to the film selection!Xiaomi official popular science UV film FAQ

IT House April 11 News There are often a variety of mobile phone film in the market, of which the most popular is UV film. However, the quality of UV films on the market is often uneven, and may even cause damage to mobile phones. Recently, the official customer service of Xiaomi mobile phone has popularized the UV film and some common problems in the Xiaomi community.

The official Xiaomi customer service said that they have recently received many feedbacks from users about problems such as button failure, button sticking, and side buttons not popping up. developed a new “UV film” in which the glue leaked into the key structure and caused the device to malfunction. The official reminds users not to buy related products when purchasing film products. If the film has been pasted and there is a problem, they should go to the after-sales service for testing as soon as possible.

What is UV film?

IT House learned that the UV film adopts the method of separating glue and outer protective glass. When applying the film, it needs to be glued onto the screen first, then put the film and squeeze the glue onto the entire screen, and then use the UV lamp to cure

However, according to Xiaomi’s official introduction, the “glue” of the UV film is actually not very sticky. in order to achieve the bonding effect.

Xiaomi officials said that this special filming method and glue design have many risks that may lead to failures in the operation. The curing range of small UV lamps is limited, and the glue may leak even when it is not fully cured, which can easily lead to the failure of peripheral devices such as buttons; at the same time, the protective glass layer and glue layer of the UV film may cause the light deviation of the fingerprint sensor. , in some cases, it will affect the normal use of fingerprint recognition.

At the same time, the design of the curvature on both sides of the curved screen Model itself will also make it easier for the liquid to contact the middle frame, and it is more likely to leak into the buttons. If the protection is not good or there is too much glue, it may leak into the earpiece, and there is a risk of the earpiece being silent or abnormal sound.

The Links:   2MBI150US-120-50 NL6448BC18-01

Lattice’s Low-Cost Layout Technology for BGA Package PLD Designs

Overview of BGA Packages

To meet changing market standards and reduce time-to-market, programmable logic devices (PLDs) are increasingly used in circuit board and system designs. The use of programmable logic devices enables faster time-to-market and greater design flexibility relative to application-specific integrated circuits (ASICs) and application-specific standard products (ASSPs). Programmable logic devices are used in many products, such as handheld devices, because of their new product architecture, which features reduced power consumption, new packaging options, and lower cost per chip. Typical programmable logic device applications include: power-on sequencing, level shifting, sequencing, interface bridging, I/O expansion, and discrete logic functions.
Increasingly complex system requirements drive the need for higher PLD logic density and more I/O pins. Therefore, Ball Grid Array (BGA) has become an optional packaging method for PLDs. BGA packaging options, such as chip-level BGA, fine-pitch BGA, and chip-array BGA, have largely replaced the quad flat pack (QFP) that is most commonly used on most PLDs. BGA is widely welcomed by system designers, mainly due to its higher I/O density, which greatly improves the pin count to board area ratio, because it has a smaller package size than the QFP package, and therefore also space Ideal for restricted applications. It saves board area and the height of the package itself. Other key benefits of BGA packaging include: better thermal performance, tighter misalignment tolerances, reliable package construction, and a proven assembly process.
Challenges for system designers
With the evolution of programmable logic devices, BGA packages are developing towards an increase in pin count and a decrease in pin pitch. Pin pitch or ball pitch refers to the distance between two adjacent pin centers or solder ball centers. Pin spacing has a significant impact on routing I/O out of the PLD. The trend toward higher pin counts and smaller pin pitches presents a huge challenge for system designers, who must use more aggressive design rules to meet design requirements through advanced stack-up and via techniques. Taken together, these factors greatly increase the cost of printed circuit boards. This article discusses some techniques that system designers can use to reduce board cost when designing PLDs in BGA packages.
Factors Affecting Printed Circuit Board Manufacturing Costs
The cost of manufacturing printed circuit boards is a major consideration for many Electronic products. Various factors that affect the cost of a printed circuit board are: the number of layers of the printed circuit board, the choice of stack-up and via technology, design rules and routing techniques.
Printed circuit board layers
The number of layers of a printed circuit board is one of the main factors affecting the cost of a printed circuit board. The term “BGA breakout” refers to the routing of the fanout and pinout around the device prior to the normal routing of the printed circuit board. BGA breakout is the most important factor affecting the number of layers in a printed circuit board. The PCB layer count can be minimized by choosing the appropriate BGA breakout mechanism, stackup Model and via technology. Most programmable logic device suppliers offer BGA breakout tips to assist with board design and layout. These tips help optimize printed circuit board manufacturing and reduce costs.
Stackup and Via Models
The choice of stack-up and via model has the greatest impact on reducing PCB layer count and manufacturing cost. There are two main stack-up technologies – FR-4 lamination and High Density Interconnect (HDI). FR-4 Laminate Laminate technology is used in larger circuit designs such as computer motherboards. HDI is more suitable for space-constrained applications such as handheld devices.
Multilayer printed circuit boards use vias or plated through holes to transmit signals from one layer to another. There are four main types of vias: through holes, blind vias, buried vias (or embedded vias), and microvias.
Vias provide connections through the top and bottom layers of the printed circuit board. Blind vias provide a connection between the top or bottom layer and a layer inside the printed circuit board. Embedded or buried vias provide connections between layers inside a printed circuit board. Microvias are extremely small holes laser drilled to provide electrical connections between several layers in a multilayer circuit board. Microvias are used for HDI circuit boards.
Typically, laminate printed circuit boards with through-holes are the least expensive to manufacture, and HDI laminates with micro-vias are the most expensive to manufacture. Laminates with blind or buried vias are more expensive to manufacture than laminates with through holes and less expensive than HDI laminates with microvias. There are several new technologies now, using epoxy fill and tin film to cover the vias, which also increase the cost of the circuit board.
design rules
Design rules affect manufacturing yield and performance. Manufacturing costs are increased when more aggressive design rules are applied. Two examples of design rules are as follows. These two design rule examples use a Lattice MachXO PLD (LCMXO640-M132/MN132) in an 8x8mm, 0.5mm pitch, 132-ball csBGA package. In each example, the MachXO PLD is placed on a 4-layer stackup circuit board. Note that Example 1 adopts the more aggressive design rule of Scale 2. Therefore, the cost of the printed circuit board to meet the design rules in the first example will exceed that of the board in the second example.
Most PLD suppliers provide design rules as shown in the table below. These design rules help reduce manufacturing costs and are supported by most printed circuit board manufacturers.
Table 1: Lattice semiconductor Recommended SMD Pads for Different Lead Pitch Packages
Table 2: Lattice Semiconductor Recommended for 0.8mm Lead Pitch caBGA Package
Design Rules for MachXO and ispMach4000ZE Devices
Wiring Tips
Once the proper stack-up technique, via model, and design rules are selected, the Fanout via pattern becomes the most important factor affecting the number of layers on a board using BGA breakout technology. Here are a few tips to help keep costs down:
Bringing out the pins around the device allows more pins to be routed on the same layer. When using a BGA with a pin pitch of less than 0.8mm, draw the fanout vias of the first two rows of pins around the device and as far away as possible from the BGA package. Bringing them further apart allows the last two rows of pins to be drawn out and routed on the same layer. This will help reduce PCB layers and manufacturing costs.
Use North, South, East, West (NSEW) or layer-heavy traces to improve efficiency. When only 2 to 4 layers are available for BGA routing, it is reasonable to lead out to each layer in all directions (also known as NSEW routing) due to the extremely high routing density. However, when the wiring that can be used for BGA exceeds 4 layers, the concept of emphasis on layers is used, that is, the lead-out wiring conforms to the emphasis on layers, which can lead to more efficient wiring.
The four-quadrant dog-bone routing method is used to increase the routing density. When routing pins in all directions on a layer, routing can be facilitated if the routing and via patterns (also known as dog-bone) have different orientations in different quadrants. This is an efficient way to increase wiring density. The figure below shows an example of a four-quadrant dog-bone wiring.
Figure 1: Example of a four-quadrant dog-bone style fanout for the ispMACH 4000ZE (LC4256ZE-MN144) in a 7x7mm, 0.5mm lead pitch, 144-ball csBGA package.
Note that the four-quadrant dog-bone routing increases the routing channels for rows and columns at the quadrant center origin. This space can be used for routing more signals. On the board, the column and row routing channels are suitable for placing add-on capacitors and pull-up resistors. Four-quadrant dog-bone routing has lower cost and lower risk of soldering issues than via-in-pad.
Use in-pad vias to provide space for outgoing pin routing. The space between the pads and the pads can be reserved for the routing of other signals by using the via-in-pad method. As the name suggests, the center of the BGA ball pad can be made into a through hole. Figure 2 demonstrates this technique.
Figure 2: Example of lead routing using in-pad vias for a MachXO PLD (LCMXO640-M132/MN132) in an 8x8mm, 0.5mm lead pitch, 132-ball csBGA package.
The three rows of BGA ball pads are shown in the figure. The middle row uses in-pad vias. This technique is most useful when assembling power or ground planes because it implements a continuous power or ground plane beneath the BGA. When using in-pad vias, we must keep in mind that the backside of the board below the BGA has less space available for capacitors and resistors due to the way the pins are routed from the fanout and vias.
Align blind vias to increase routing density. When blind vias are used, aligning blind vias in row and column directions is a very effective way to increase routing density. It is most effective especially when a BGA with a high pin count is used, and at this time, drawing out the device pins is the main factor affecting the number of layers on the circuit board.
Use microvia HDI stack-up technology to reduce the number of circuit board layers. Micropores are inextricably linked to HDI. The use of microvias is very important to reduce the number of layers in an HDI laminate.
Summary of this article
With each generation of ball BGA packages getting smaller and smaller pin pitches, new printed circuit board manufacturing processes and signal via types need to be developed to handle the higher layout complexity. By viewing the programmable logic device ball density and pin pitch, the application’s I/O signal requirements, and the production constraints of printed circuit board manufacturing equipment, system designers can better make trade-offs between design decisions. Most programmable logic device suppliers publish printed circuit board layout tips and BGA breakout examples on their websites. System designers can use this information to reduce printed circuit board costs.
Author: Manish Garg
Lattice Semiconductor

The Links:   7MBR100SD060 PGD150S16

2022 Asia Automotive Lightweight Exhibition and Shanghai International Wheel Industry Exhibition: “Lightweight” to go into battle, come as promised

As countries implement policies that force automakers to reduce fuel consumption, vehicle lightweighting has become an important breakthrough for major automakers. In the overall plan for automobile development in “Made in China 2025”, it is also emphasized that “lightweight is still the top priority”, “lightweight” has become an important national strategy, and more and more research institutions and the automotive industry will The focus of its research work is on vehicle lightweighting. The 2022 Asia Automotive Lightweight Exhibition and Shanghai International Wheel Industry Exhibition hosted by Reed Exhibitions will also set sail again from July 6 to 8. This exhibition will focus on the Display of materials, processing technology, auto parts, lightweight solutions and other related products related to automotive lightweighting, focusing on new materials, new technologies and new processes for automotive lightweighting.

Highlight 1: Resource sharing during the five exhibitions, centralized Display of the entire industry chain

It is understood that the 2021 Asia Automotive Lightweight Exhibition and the Shanghai International Wheel Industry Exhibition will be held at the same time as the 16th China International Aluminum Industry Exhibition. The three exhibitions have attracted a total of 20,105 domestic and foreign professional visitors during the same period, and more than 500 companies in the industry participated in the exhibition. In 2022, it will also be held in the same place as the 17th Shanghai International Automobile Manufacturing Technology and Equipment and Materials Exhibition and the 17th Shanghai International Industrial Assembly and Transmission Technology Exhibition, to fully display the upstream and downstream related innovative technologies and technologies of the automotive industry chain. product.

As a focus on displaying lightweight raw materials, auto parts, processing technology and structural optimization and other related products and design solutions , Boao Magnesium Aluminum, Wanfeng Aowei, Lizhong Group, Kingfa Technology, Wanhua, Covestro, Shandong Double One, Grid and other enterprises actively participated.

Well-known domestic and foreign auto companies, new automakers, and parts manufacturers will also come to visit. The heads of core departments such as procurement, technology research and development, and management of vehicle and parts companies will visit and negotiate on site.

Highlight 2: Professional subdivision forum to discuss industrial changes and trends together

Under the background of carbon emission reduction and the development of new energy, the new energy vehicle industry has entered a golden period of development. According to data released by the China Automobile Association, the cumulative sales of new energy vehicles in my country from January to November 2021 reached 2.99 million units, and it is expected that the development prospects of the new energy vehicle market will be bright in the future. In the face of the rise of new energy vehicles and the rapid changes in technology, in 2022, the organizer will specially plan the “Third Forum on Innovative Application of Automotive Lightweight Technology and Related Materials – New Energy Vehicles”, focusing on the concern of OEMs and parts companies We invite domestic first-tier OEMs and first-tier supporting enterprises to share with us and discuss the future solutions of lightweighting. Expand new elements of automotive lightweight.

The organizer of the exhibition will also join hands with the China Association of Automobile Manufacturers and the Wheel Branch to hold the “Third Wheel Equipment Technology Exchange Conference” and “2022 Wheel Standard Training Conference”. At the same time, this exhibition will continue to hold the “Power of Colleges and Universities” activity, and invite domestic famous colleges and universities to participate in the “Second College Innovation Achievement Technology Exchange Conference and Innovation Achievement Exhibition Area” to discuss the innovative materials and processes of colleges and universities in automobile manufacturing. Achievements, focusing on showing the excellent cases of universities in the field of lightweight and the practical results of school-enterprise cooperation, bringing scientific research results into practice through the “University Power” activity, promoting the integration process of “industry-university-research”, and promoting the positive development of the industry. The tight collection of lightweight key core technologies promotes the rapid implementation of key technologies.

Highlight 3: Create a lightweight innovation area again, covering a variety of materials and technologies

In order to achieve the development goal of “low energy consumption” in the automobile industry, on the premise of ensuring the performance of the automobile, “reducing the weight” of the automobile has become an urgent issue for the automobile industry. tuyere”. The organizer will continue to build the “Fourth Lightweight Innovation Achievement Exhibition Area”, which has attracted many companies including Beifang Lingyun, Chinalco Ruimin, Kunfu, Yuli, Aosheng, and Kenuo to appear in the exhibition area. Jointly display innovative automotive lightweight technologies and application products.

At the same time, this exhibition will cooperate with China Composites Industry Association to jointly create a “Automotive Lightweight Composite Materials Zone”, focusing on the development of composite materials in automotive body structure and parts and the application of composite material design concepts in automotive lightweighting. Innovative applications, jointly explore low-cost material systems and low-cost manufacturing process development opportunities, and provide automotive users with more diversified material choices!

Highlight 4: Subdivide the different needs of buyers, and carry out online and offline trade matching throughout the year

2022The Asia Automotive Lightweight Exhibition and Shanghai International Wheel Industry Exhibition will subdivide the registered visitors, and provide 365-day supplier recommendation and introduction services throughout the year based on the audience’s purchasing needs and products of interest, so as to select high-quality suppliers for enterprises. At the same time, the organizer will also invite domestic and foreign well-known vehicle enterprises, parts supporting enterprises and other end users with purchasing decision rights to conduct one-on-one exchanges and negotiation with exhibitors, and carry out the “Automotive Purchasing Project Matchmaking Conference – Aluminium Lightweight Special Session” , “Export Trade Matching Meeting”, to build an online and offline business exchange platform to help exhibitors and visitors connect efficiently, and bring efficient and win-win exhibition and visit benefits to exhibitors and visitors.

2022The Asia Automotive Lightweight Exhibition and the Shanghai International Wheel Industry Exhibition have fully set sail, and the audience’s “online pre-registration” has been fully opened. You can pre-register online through the official website, WeChat and other methods to meet industry leaders and professionals July Shanghai, to discuss new opportunities for the future development of automotive lightweight!

For exhibition related matters, please contact

Ms. Xing Jiahui

Tel: 010 5933 9387


The Links:   6MBP50VBA120-50 FZ3600R17HE4

Xinye Electronic Automotive Lighting and Infrared Shanghai Session was successfully held!

A grand meeting was held at the Great Wall Holiday Hotel in Shanghai Plaza. The meeting was jointly sponsored by Xinye Group and Osram Opto Semiconductors, and hosted by OFweek semiconductor Lighting Network. The theme of the meeting was “Automotive Lighting and Infrared”. This conference is the second series of seminars that will be relocated to Shanghai after Xinye Electronics and Osram jointly successfully held a seminar in Chengdu. With practical and professional themes, it attracted many industry professionals to attend.

Shanghai conference scene

At the beginning of the meeting, Lin Junwei, the marketing director of Xinye Electronics, briefly described the theme of the meeting, and made a general interpretation of the current situation and future trends of the development of the automotive lighting market. With the rapid development of the whole vehicle LED and ADAS, the LED automotive lighting market will continue to maintain its incremental advantages, and the market space will be broader.

Lin Junwei, Marketing Director of Xinye Electronics

Subsequently, Dou Mingjie, Senior Marketing Manager of Osram Opto Semiconductors, carried out the theme of “Automotive LED Application Trends and Innovative Products”. Dou Mingjie described the development history of Osram Opto Semiconductors as the industry leader, and then shared his insights on the future market and products of LED automotive lighting. From the perspective of style design and visual performance, more comfortable, more personalized, more creative development trends, more fluid rhythm and more convenient and safe products can meet future needs. Finally, for the application of LED lighting inside and outside the car, he shared many cases of cooperation between Osram and car companies around the world.

Dou Mingjie, Senior Marketing Manager, Osram Opto Semiconductors

Then, Chen Yan, senior manager of automotive applications in the Asia-Pacific region of Osram Opto Semiconductors, talked about the evolution of ADB headlights from low pixels to high pixels. According to the different requirements of AFS/ADB, LED can be realized. Active LED arrays have developed by leaps and bounds from low pixels to 10K high pixels, and have the characteristics of high efficiency and flexibility.

Chen Yan, Senior Manager, Automotive Applications, Asia Pacific, Osram Opto Semiconductors

After a relaxing activity segment and coffee break. Lu Huancai, Asia Pacific Marketing Manager of Osram Opto Semiconductors Infrared/Laser/Sensor Division, gave a keynote speech focusing on the application of Osram’s infrared and laser sensors in ADAS technology. The application of infrared light-emitting diodes and sensors, lidar, a key device in autonomous driving, and visible laser applications were explained.

Lu Huancai, Asia Pacific Marketing Manager, Infrared/Laser/Sensor Division, Osram Opto Semiconductors

The last speech of the conference was brought by Wang Technology, technical support engineer of Xinye Electronics, and the theme was TI (Texas Instruments) high-performance automotive LED driver solutions. The current detection of the internal chip drive circuit, as well as the cost, size, power, electromagnetic characteristics, etc., will be explained.

Xinye Electronic Technical Support Engineer Wang Technology

In addition to the wonderful speech, Xinye specially prepared a demonstration prototype for the audience. During the interval of the meeting, various prototypes attracted the audience to stop and watch.

The Links:   LJ640U35 NL3224AC35-10

The role of human digitization, it will bring a new world of future medicine

How wonderful is the human body? Under the skin of 4.5 square meters, we have 3 million sweat glands and 16 million hair follicles. Our heart is like a perpetual motion machine, constantly contracting and expanding to transport blood. We know that the academic world has been working on the digitization of the brain, so is the digitization of the human body also valuable? Can we simulate every tendon, nerve and even all cells to explore the mysteries of human growth and aging?

Digitizing the human body does not seem to be that difficult compared to a complex brain with an innumerable number of neurons. So what step has our human body digitization reached today? What role can it play? Basically, the human body digitization is divided into three steps. The first step is physical digitization, the second step is physiological digitization, and the first The third step is the digitization of intelligence. Physical digitization is to synthesize the three-dimensional pattern of the human body structure in the computer, and restore every bone and organ in detail. When calling and viewing it in the computer, it is like dissecting a corpse.

Physiological digitization is to track various improvement data of the human body, from heart rate, body temperature to blood pressure and blood sugar, etc., and strictly record the physiological response of human functional applications, so that the human body can be “alive” in the digital world. As for the digitization of intelligence, the concept is very close to the analog brain, mainly to understand how human consciousness works. With the above steps, you can collect dynamic and static multi-source data on the real human body, and build a digital human body through geometric, physical, physiological and intelligent modeling.

At present, the digitization of the human body is in the first and second steps, and the third step is relatively far away. First of all, we can take a look at how the physical digitization of the human body is realized. It is a bit scary to say that the physical digitization of the human body is achieved by freezing the human remains and then slicing them. Only in this way can the human body be accurately restored to a digital image.

Globally, the United States is the first country to start this program. Preparations began in 1986 until 13 years later, in 1993, when a male death row inmate participated in the project. At that time, there was a lot of controversy about the identity and voluntary nature of the remains. In 1994, a woman who died of a heart attack joined the program, and it remains a mystery whether she volunteered or not. The two bodies were cut into 1-millimeter and 0.33-millimeter slices, respectively, and recorded as CT, MRI and anatomical images, making the data available to 4,000 medical institutions around the world.


In the digitization of the physical human body, the most famous volunteer is a woman named Susan Porter. After she learned that she had cancer in 2000, she took the initiative to contact relevant institutions and said she was willing to donate her body. For the next 15 years, she toured the future where she would handle her own scalpel and cutter, and even mingled with the participating medical students. When he passed away in 2015, the technology of digitizing the physical human body has also made great progress. Susan’s body was cut into 27,000 pieces, which is the most delicate processing method so far. Now medical institutions are delineating and labeling Susan’s various tissues, organs, blood vessels, etc., and more detailed digital human data will be released in the future.

In contrast, the biological digitization of the human body is immature and is mostly dominated by mobile health startups. Larry Smarr, a professor at the University of California, is a supporter of digital human body records. He wears a device on his belt every day to record 150 items of data such as his heartbeat, blood pressure, exercise volume, etc. in different states. In addition to this, he records his blood indicators and intestinal flora data once a month.

Combining these data, Larry Smarr believes that he can quantify his life status through calculation, like building a car dashboard, so as to know when it is time to “maintain the car”. What’s more, an entrepreneur from Oakland has been recording his physical signs since fifteen years ago, and even faithfully recorded his heart rate during the first kiss.

According to a survey by the Pew Research Center, 75% of people who use a physical sign recording device such as a wristband are willing to share their data with others. Apple’s ResearchKit, once launched, also advocates that users of various Parkinson’s, diabetes, heart disease and other applications around the world share data for research. In just three days after ResearchKit was launched, more than 41,000 people voluntarily participated in data sharing.

While users themselves don’t mind data sharing, the process itself is legally sensitive and time-consuming. At the same time, some scientists said that recording their own physical symptoms data all the time can easily lead to neurosensitivity and hypochondriasis. It is not known whether to rely on their own physiological natural reactions to judge the health status, or rely on the data on the device.

From a physical point of view, the digitalization of the human body perfectly solves the shortage of medical anatomy resources. Anatomy of a corpse is an irreversible process in itself, which is in short supply in medical institutions and medical schools. With a digitized human body, the process of dissecting and “recovering” can be repeated indefinitely. Especially when combined with VR and AR technologies in the future, these data-based human bodies can play more roles in teaching and scientific research. Perhaps medical students no longer need to be surrounded by laboratories, and can conduct remote scientific research work and study through VR glasses from all over the world.

Physiologically speaking, the digitization of the human body can play a role in experiments with drugs, treatments, and more. Through the recording of human body sign data, the life style and physical condition can be mapped through machine learning, and the relationship between sleep, exercise, etc. and physical health can be mapped, so as to provide reasonable lifestyle guidance. If the physical simulation at the molecular and cell level can be realized, virtual experiments and clinical experiments of drugs can be carried out, which can greatly reduce the drug development cycle and reduce the need for human testing drugs.

Of course, the digitization of the human body means the processing and transmission of massive data, all of which are also based on the support of machine learning, 5G transmission, cloud platforms and other technologies. Compared to more complex brain simulations, human digitization is already on the way. It is believed that in the near future, those who selflessly contribute remains and data to the digitization of the human body will be able to play more value in the history of human medical development.

The Links:   KT224510 PM400DSA060 IGBTMODULE

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