Optimizing Automotive Infotainment and Infocomm Systems with FPGA Coprocessors

High-end automotive infotainment systems that integrate data communications, local services and video entertainment functions require high-performance programmable processing technology support. Integrating FPGA co-processors into mainstream automotive infotainment system architecture is the most ideal solution. This paper presents the requirements of an automotive entertainment system, discusses the mainstream system architectures, and describes how FPGA coprocessors can be integrated into hardware and software architectures to meet high-performance processing requirements, flexibility requirements, and cost reduction goals.

Entertainment electronics are becoming a major aspect of differentiation among luxury vehicles, driving a rapid evolution in performance and functionality. How to compromise performance, cost and flexibility requirements is a challenge for design engineers. High-end applications include satellite radio, rear seat entertainment, navigation, various types of audio playback, speech synthesis and recognition, and other new applications.

The core technology used in car entertainment systems is fundamentally different from traditional car applications. Unlike other areas of automotive electronics, these entertainment applications are used every day and requirements are constantly changing. In addition, outdated entertainment systems will be a major barrier to new car sales and will affect car resale and rental prices.

Technical requirements for in-vehicle entertainment systems

Traditional automotive electronics are driven by comprehensive standardization with longer product life, wider temperature range, and lower cost requirements, which in-vehicle entertainment systems must also meet. Design engineers not only need to design long-life systems, but also need to be able to adapt to the rapid development of system functions. These requirements require a high degree of flexibility and performance, which cannot be provided by traditional application-specific standard product (ASSP)-based system architectures.

The basic architecture of in-vehicle entertainment systems designed today can support flat-Panel displays, and can Display dynamic maps and car information through a graphical human-machine interface. These architectures are surrounded by highly standardized microcontrollers, various standard interfaces, and simple hardware accelerators that support low-end graphics processing. This architecture can meet the requirements of mid-level entertainment systems in the automotive market at a very low cost, and can also be extended to high-end applications to meet the requirements of the top luxury car market. Video image processing and communication are typical top-level application examples. The various standards supporting these applications include MPEG2, MPEG4, and H.264 for video, and GSM/EDGE, WCDMA, 1XEVDO, satellite radio, satellite TV, digital video broadcasting, and WiFi for communications, all of which rely on evolving multiple Signal processing algorithms that require particularly high programmable processing performance.

There are three semiconductor technologies currently available for implementing these highly complex algorithms: Programmable Digital Signal Processors (DSPs), ASSPs, and Field Programmable Gate Arrays (FPGAs). DSP is a high-performance programmable processor specially designed for signal processing. DSP processors have high flexibility, low power consumption, and high cost performance, but without hardware acceleration, they cannot provide today’s advanced image processing and wireless communication algorithms. The required computing power; usually ASSPs with built-in DSP processors can provide optimized solutions for simple video or communication standards, but cannot be programmed to adapt to different standards; while FPGAs not only have high processing performance, but also programmable, Therefore, a wide variety of applications and standard requirements can be met. Unlike the other two technologies, the flexibility and performance of FPGAs can meet the requirements of all potential algorithms.

Optimizing Automotive Infotainment and Infocomm Systems with FPGA Coprocessors

Figure 1

Application of FPGA Coprocessor

The basic architecture of information communication mentioned above requires additional processing chips to handle high-end applications. These chips are generally ASICs and ASSPs, which are integrated with the processor through a memory or video processing bus to become application-specific coprocessors. Replacing this application-specific hardware with an FPGA is a very good approach, and an application that integrates an FPGA and a processor is called FPGA co-processing. This use of the FPGA can assist in any high-performance application by downloading new application-specific accelerators into the FPGA upon request. This concept is widely used in advanced military multi-standard radio equipment, commonly referred to as software-defined radio (SDR) technology. With SDR technology, a radio can be automatically adapted to different radio standards at the touch of a button, which not only helps future-proof the device, but also reduces the number of custom processors idling for different tasks. This software radio technology can also be used for in-vehicle communication and video applications.

The flexibility of FPGAs in video processing and wireless connectivity also saves equipment costs and adds value to the system. The current basic architecture requires ASSPs to support every new video codec or wireless standard. Replacing multiple ASSPs with a single FPGA can reduce the number of times the vehicle must be configured and maintained during its lifetime. Extending the basic architecture of an in-vehicle entertainment system to include FPGAs provides a single, high-end platform that can be programmed to cover a wider range of video and wireless standards and performance. This approach is equally suitable for use in advanced automotive entertainment system architectures.

Delphi Delco Electronic Systems has released an advanced example of an automotive entertainment system architecture. Using a standard SH-4 microprocessor and a Hitachi HD64404 “Amanda” ASIC device, the platform provides the basic functions required by 80% of the mid-level automotive market. The system provides a general-purpose control processor with a standard API layer that abstracts hardware peripherals and coprocessors. ASIC provides basic peripheral device functions and an integrated graphics processor, which can support interactive graphics and extended functions, but cannot provide video codecs or other DSP functions. The system provides the basic functions required by all entertainment devices, but still requires an additional ASIC or ASSP for video codec and wireless communication.

Optimizing Automotive Infotainment and Infocomm Systems with FPGA Coprocessors

Figure II

The Amanda chip in the Delphi architecture (see Figures 1 and 2) uses two processing buses, namely the Pixel bus for high-performance data streams such as video processing and the register bus for control, both of which are connected to the SH-4 MPX bus and external memory interface. This perfect combination of bus and memory interfaces can well support flexible video codec and wireless communication platforms based on FPGA coprocessors.

FPGA co-processing enables the FPGA to be tightly integrated with the control or DSP processor, so it can offload most of the algorithmic processing tasks while retaining the standard programming interface on the control processor. This integration works best when the main data flow of the algorithm resides on the FPGA or associated memory. The algorithm is controlled by slow control signals from the control processor.

This type of architecture can be applied to wireless communications, which can support digital processing in GSM/EDGE, WCDMA, 1xEVD0, and various 802.11 standards through a single FPGA. Other solutions can only be specialized hardware design for each standard, but doing so will multiply the cost and board area.

In addition, after applying FPGA co-processing in image processing, a single FPGA can complete multi-standard video codecs including MPEG2, MPEG4 and H.264. In fact, the same FPGAs used in wireless communication applications can be used here.

The FPGA coprocessor integrates with the processor-based system through a direct memory access (DMA) interface. The software layer running on the embedded processor provides an application interface for each coprocessor, and each coprocessor has an initialization routine that loads the FPGA with the correct application coprocessor. After application initialization, software calls the coprocessor to control parameters, timing, and data flow in and out of the coprocessor. Depending on the specific implementation standard, there may be a high level of interaction between the FPGA coprocessor and the control processor, or the FPGA coprocessor may work completely independently. In this case, the control processor simply loads the algorithm and then runs on its own.

Each program image loaded into the FPGA needs to be integrated into the peripheral system. The programmable functionality of an FPGA requires a well-defined system interface, since every FPGA-based accelerator depends on it to communicate. Often FPGAs will have multiple interfaces to connect controllers, memories, and other peripherals or connectors. An FPGA may simultaneously contain multiple coprocessors that share an interface to the control processor. Each peripheral or coprocessor can have additional buses for high-performance data flow processing.

In a video codec, there is generally one input source and one output destination. The video input interface in the Delphi system architecture is part of the Amanda ASIC and uses the ITU-R BT.656 interface for video streaming. This interface can later be extended and managed by an ASIC to suit different kinds of displays. The FPGA may need to be connected to 2 other buses, the memory bus on the ASIC chip and the PCI/MPX bus of the main control processor. With these three connections, the FPGA can support high-bandwidth video and communications applications.

FPGAs can complement the main processor by providing a reprogrammable platform for application-specific processing architectures. However, FPGA programs are fundamentally different from programs for standard processor architectures. FPGAs can provide high-performance hardware structures with programmable logic cells, routing resources, DSP processing blocks, memory, and I/O. The system architecture execution mode of FPGA is basically the same as that of standard ASSP, that is, some special functions of the system are designed and realized through hardware and software development tools. The output of these tools is a binary image file that, when loaded into an FPGA, will determine the functionality of all programmable logic cells, routing resources, DSP processing blocks, and so on. The host processor can load these binary images into the FPGA during system operation. Various program images can be created to support MPEG2, MPEG4, H.264, GSM/EDGE, WCDMA, 1xEVDO, GPS, 3D graphics accelerators or other algorithms that may be used in automotive telematics systems. Depending on the user’s menu selections in the entertainment system, specific applications can be downloaded into the FPGA by the main processor and then controlled by the main processor.

FPGAs are used for programmable functions requiring well-defined system interfaces

Control of a particular hardware accelerator by the host processor is generally accomplished through registers and a memory interface, each register controlling some aspect of the hardware accelerator’s operation. This is the default co-chip in a Delphi system, and it will be the same for every co-processor architecture loaded into the FPGA. With FPGAs, it is easy to handle tasks like standardizing registers and memory interfaces to control coprocessors programmed into the device. This standard interface defines how to read and write data to and from the coprocessor, how to start and stop reading and writing, how to reset, and contains a set of registers that control application-specific operation. All of these registers are part of the FPGA’s internal linear address map, so software physical device drivers can easily access these registers.

Software physical device drivers for coprocessors have a higher level of abstraction than register interfaces implemented in hardware. The software driver provides the mapping from the system’s algorithm parameters to the control registers, so the application software is very easy to write and maintain. Higher-level Model device drivers remain fairly portable across changes in the underlying hardware implementation. The software architecture in a Delphi system can support software or hardware co-processors to implement algorithms, and it provides several abstraction layers that separate the algorithm implementation in software or hardware from the physical implementation. FPGA coprocessors fit perfectly into Delphi’s software and hardware architecture.

FPGAs are designed to be used in many systems with a basic architecture similar to that of Delphi systems. These systems contain more than one control or DSP processor and utilize FPGAs to accelerate tasks that require high-performance processing. The key challenges in implementing an FPGA coprocessor lie in the following aspects: designing different hardware accelerators for use in the FPGA; integrating the hardware accelerator with an external control processor; and creating a software layer that controls the hardware accelerator. All required hardware accelerators include mainstream algorithms for video and communications applications. There will be a broad market for such applications in the future, and the development of this market will foster more specialized design companies of special standard intellectual property (IP) hardware accelerators, which can provide off-the-shelf products that can be directly used in advanced low-cost FPGAs. algorithm. In addition, commercial IP modules designed for MPEG2, MPEG4, H.264, WiFi, and other video and communication standards can be purchased. Figure 3 is the block diagram of the MPEG4 decoder IP module introduced by Amphion, which can be used in ASIC or FPGA.

Optimizing Automotive Infotainment and Infocomm Systems with FPGA Coprocessors

image 3

Application of SOPC Builder

The next step is to integrate the hardware accelerators in the FPGA with external buses for control, data input and output. Design engineers can easily do this with new development tools. Design engineers can use the SOPC Builder, a system integration tool provided by Altera, to select the appropriate IP module from the available IP list. When selected, the tool provides a parameterization menu that allows the user to control different architectural options prior to implementation. Once parameterized, the module is included in the list of other peripherals and processors that the engineer is ready to integrate. After each IP block is selected and parameterized, it needs to be integrated into the processing architecture.

SOPC Builder enables design engineers to define high-performance switch architectures that connect various hardware accelerators and peripheral devices with external host processors. The definition of this switch architecture is done with a mouse click on an intuitive matrix diagram of module interconnections. After the definition, SOPC Builder can automatically combine each IP, and then generate the description of the hardware description language, and automatically synthesize the final FPGA program. The final program is downloaded to the FPGA during runtime, implementing a coprocessor for a specific algorithm.

After hardware integration is complete, software physical devices are required to separate high-level software control from the specific registers and memory-mapped architecture used to control the hardware accelerator. The registers and memory used to control the hardware accelerator are standard components of parameterized IP blocks. However, the integration of multiple peripherals and accelerators requires a single register and memory map that implements all programmable features on the FPGA. SOPC Builder can automatically create such registers and memory maps when assembling IP into a user-defined switch fabric.

Each IP module contains a set of predefined software physical device drivers, which are mainly used for the control of the IP module by the external host processor. SOPC Builder automatically assembles individual software-physical device drivers and automatically associates each driver with the registers and memory maps associated with the IP blocks it controls. So SOPC Builder can automatically create and integrate the hardware and software architecture of the FPGA coprocessor and control processor in this way. SOPC Builder can meet the performance requirements of FPGA’s rapid development, and adapt to FPGA’s ability to continuously enhance the application in complex system implementation.

Factors driving the rapid development of FPGA technology

Programmable logic devices have grown rapidly since their introduction 20 years ago, from low-level glue logic to the lowest cost, highest programmable processing performance devices available today. Two key factors driving FPGA performance and cost are the evolution of FPGA architecture and the way FPGAs use semiconductor technology. The programmable logic cell array provided by the FPGA fabric is combined with programmable routing resources. In early low-density FPGAs, this architecture enabled the interconnection of simple processing units. As FPGA densities increase, array architectures can provide highly parallel processing capabilities. At present, the entire processing array of FPGA architecture includes memory modules, DSP modules and programmable I/O, so it can easily meet the performance requirements of automotive information processing systems.

Another important driver of FPGA development is process technology and its impact on performance and cost. Using the latest generation of process technology can increase the density and performance of FPGAs and reduce the cost of FPGAs. At the same time, the wide application of FPGA in turn promotes the development of process technology. FPGAs are extremely valuable to the development of semiconductor process technology because they use regular structures that can be put into volume production early in their life cycle. The regular structure of FPGAs facilitates the collection of statistical data in product defect testing, which is important for fine-tuning process technology to achieve higher manufacturing yields. The symbiotic relationship between FPGAs and process technology continues to increase FPGA density and reduce device cost. Therefore, relative to special-purpose ASICs and ASSPs, Altera’s Cyclone series of low-cost FPGAs are very competitive in price.

Summary of this article

The technology and differentiation of automotive entertainment systems is constantly evolving at a rapid pace. The advanced system architecture serves most mainstream automotive markets and enables high-end product differentiation through additional ASSP and software support. FPGAs provide a high-performance and flexible co-processing platform and integrate many ASSP functions into a reprogrammable platform. FPGA coprocessors are well suited for mainstream automotive entertainment architectures such as the Delphi architecture. By using FPGA coprocessors as part of a high-end automotive entertainment system architecture, automotive companies can program software to provide a variety of high-end video and communications capabilities that ASSPs cannot provide alone. A flexible high-end automotive entertainment architecture leverages FPGAs to enable new capabilities throughout the car’s sale and even the life of the car. The ability to enhance the functionality of a car’s entertainment system at the sale and after-sale stages can increase the value of a car during and after the sale, while the resale value of previously leased cars remains a major source of profit for automakers.

The Links:   TD180N16KOF LM64C031 BSM150GT120DN2