Overview of BGA Packages
To meet changing market standards and reduce time-to-market, programmable logic devices (PLDs) are increasingly used in circuit board and system designs. The use of programmable logic devices enables faster time-to-market and greater design flexibility relative to application-specific integrated circuits (ASICs) and application-specific standard products (ASSPs). Programmable logic devices are used in many products, such as handheld devices, because of their new product architecture, which features reduced power consumption, new packaging options, and lower cost per chip. Typical programmable logic device applications include: power-on sequencing, level shifting, sequencing, interface bridging, I/O expansion, and discrete logic functions.
Increasingly complex system requirements drive the need for higher PLD logic density and more I/O pins. Therefore, Ball Grid Array (BGA) has become an optional packaging method for PLDs. BGA packaging options, such as chip-level BGA, fine-pitch BGA, and chip-array BGA, have largely replaced the quad flat pack (QFP) that is most commonly used on most PLDs. BGA is widely welcomed by system designers, mainly due to its higher I/O density, which greatly improves the pin count to board area ratio, because it has a smaller package size than the QFP package, and therefore also space Ideal for restricted applications. It saves board area and the height of the package itself. Other key benefits of BGA packaging include: better thermal performance, tighter misalignment tolerances, reliable package construction, and a proven assembly process.
Challenges for system designers
With the evolution of programmable logic devices, BGA packages are developing towards an increase in pin count and a decrease in pin pitch. Pin pitch or ball pitch refers to the distance between two adjacent pin centers or solder ball centers. Pin spacing has a significant impact on routing I/O out of the PLD. The trend toward higher pin counts and smaller pin pitches presents a huge challenge for system designers, who must use more aggressive design rules to meet design requirements through advanced stack-up and via techniques. Taken together, these factors greatly increase the cost of printed circuit boards. This article discusses some techniques that system designers can use to reduce board cost when designing PLDs in BGA packages.
Factors Affecting Printed Circuit Board Manufacturing Costs
The cost of manufacturing printed circuit boards is a major consideration for many Electronic products. Various factors that affect the cost of a printed circuit board are: the number of layers of the printed circuit board, the choice of stack-up and via technology, design rules and routing techniques.
Printed circuit board layers
The number of layers of a printed circuit board is one of the main factors affecting the cost of a printed circuit board. The term “BGA breakout” refers to the routing of the fanout and pinout around the device prior to the normal routing of the printed circuit board. BGA breakout is the most important factor affecting the number of layers in a printed circuit board. The PCB layer count can be minimized by choosing the appropriate BGA breakout mechanism, stackup Model and via technology. Most programmable logic device suppliers offer BGA breakout tips to assist with board design and layout. These tips help optimize printed circuit board manufacturing and reduce costs.
Stackup and Via Models
The choice of stack-up and via model has the greatest impact on reducing PCB layer count and manufacturing cost. There are two main stack-up technologies – FR-4 lamination and High Density Interconnect (HDI). FR-4 Laminate Laminate technology is used in larger circuit designs such as computer motherboards. HDI is more suitable for space-constrained applications such as handheld devices.
Multilayer printed circuit boards use vias or plated through holes to transmit signals from one layer to another. There are four main types of vias: through holes, blind vias, buried vias (or embedded vias), and microvias.
Vias provide connections through the top and bottom layers of the printed circuit board. Blind vias provide a connection between the top or bottom layer and a layer inside the printed circuit board. Embedded or buried vias provide connections between layers inside a printed circuit board. Microvias are extremely small holes laser drilled to provide electrical connections between several layers in a multilayer circuit board. Microvias are used for HDI circuit boards.
Typically, laminate printed circuit boards with through-holes are the least expensive to manufacture, and HDI laminates with micro-vias are the most expensive to manufacture. Laminates with blind or buried vias are more expensive to manufacture than laminates with through holes and less expensive than HDI laminates with microvias. There are several new technologies now, using epoxy fill and tin film to cover the vias, which also increase the cost of the circuit board.
Design rules affect manufacturing yield and performance. Manufacturing costs are increased when more aggressive design rules are applied. Two examples of design rules are as follows. These two design rule examples use a Lattice MachXO PLD (LCMXO640-M132/MN132) in an 8x8mm, 0.5mm pitch, 132-ball csBGA package. In each example, the MachXO PLD is placed on a 4-layer stackup circuit board. Note that Example 1 adopts the more aggressive design rule of Scale 2. Therefore, the cost of the printed circuit board to meet the design rules in the first example will exceed that of the board in the second example.
Most PLD suppliers provide design rules as shown in the table below. These design rules help reduce manufacturing costs and are supported by most printed circuit board manufacturers.
Table 1: Lattice semiconductor Recommended SMD Pads for Different Lead Pitch Packages
Table 2: Lattice Semiconductor Recommended for 0.8mm Lead Pitch caBGA Package
Design Rules for MachXO and ispMach4000ZE Devices
Once the proper stack-up technique, via model, and design rules are selected, the Fanout via pattern becomes the most important factor affecting the number of layers on a board using BGA breakout technology. Here are a few tips to help keep costs down:
Bringing out the pins around the device allows more pins to be routed on the same layer. When using a BGA with a pin pitch of less than 0.8mm, draw the fanout vias of the first two rows of pins around the device and as far away as possible from the BGA package. Bringing them further apart allows the last two rows of pins to be drawn out and routed on the same layer. This will help reduce PCB layers and manufacturing costs.
Use North, South, East, West (NSEW) or layer-heavy traces to improve efficiency. When only 2 to 4 layers are available for BGA routing, it is reasonable to lead out to each layer in all directions (also known as NSEW routing) due to the extremely high routing density. However, when the wiring that can be used for BGA exceeds 4 layers, the concept of emphasis on layers is used, that is, the lead-out wiring conforms to the emphasis on layers, which can lead to more efficient wiring.
The four-quadrant dog-bone routing method is used to increase the routing density. When routing pins in all directions on a layer, routing can be facilitated if the routing and via patterns (also known as dog-bone) have different orientations in different quadrants. This is an efficient way to increase wiring density. The figure below shows an example of a four-quadrant dog-bone wiring.
Figure 1: Example of a four-quadrant dog-bone style fanout for the ispMACH 4000ZE (LC4256ZE-MN144) in a 7x7mm, 0.5mm lead pitch, 144-ball csBGA package.
Note that the four-quadrant dog-bone routing increases the routing channels for rows and columns at the quadrant center origin. This space can be used for routing more signals. On the board, the column and row routing channels are suitable for placing add-on capacitors and pull-up resistors. Four-quadrant dog-bone routing has lower cost and lower risk of soldering issues than via-in-pad.
Use in-pad vias to provide space for outgoing pin routing. The space between the pads and the pads can be reserved for the routing of other signals by using the via-in-pad method. As the name suggests, the center of the BGA ball pad can be made into a through hole. Figure 2 demonstrates this technique.
Figure 2: Example of lead routing using in-pad vias for a MachXO PLD (LCMXO640-M132/MN132) in an 8x8mm, 0.5mm lead pitch, 132-ball csBGA package.
The three rows of BGA ball pads are shown in the figure. The middle row uses in-pad vias. This technique is most useful when assembling power or ground planes because it implements a continuous power or ground plane beneath the BGA. When using in-pad vias, we must keep in mind that the backside of the board below the BGA has less space available for capacitors and resistors due to the way the pins are routed from the fanout and vias.
Align blind vias to increase routing density. When blind vias are used, aligning blind vias in row and column directions is a very effective way to increase routing density. It is most effective especially when a BGA with a high pin count is used, and at this time, drawing out the device pins is the main factor affecting the number of layers on the circuit board.
Use microvia HDI stack-up technology to reduce the number of circuit board layers. Micropores are inextricably linked to HDI. The use of microvias is very important to reduce the number of layers in an HDI laminate.
Summary of this article
With each generation of ball BGA packages getting smaller and smaller pin pitches, new printed circuit board manufacturing processes and signal via types need to be developed to handle the higher layout complexity. By viewing the programmable logic device ball density and pin pitch, the application’s I/O signal requirements, and the production constraints of printed circuit board manufacturing equipment, system designers can better make trade-offs between design decisions. Most programmable logic device suppliers publish printed circuit board layout tips and BGA breakout examples on their websites. System designers can use this information to reduce printed circuit board costs.
Author: Manish Garg
The Links: 7MBR100SD060 PGD150S16