“The first commercialization of FinFETs at the 22nm node revolutionized the manufacture of transistors—the tiny switches inside the chip’s “brain”. The channel formed by the “fins” in contact with the gate on three sides is easier to control than previous planar transistors. However, as the challenges facing the 3nm and 5nm technology nodes continue to accumulate, the utility of FinFETs has reached its limit.
By: Dr. Nerissa Draeger, Fanlin
The first commercialization of FinFETs at the 22nm node revolutionized the manufacture of transistors—the tiny switches inside the chip’s “brain”. The channel formed by the “fins” in contact with the gate on three sides is easier to control than previous planar transistors. However, as the challenges facing the 3nm and 5nm technology nodes continue to accumulate, the utility of FinFETs has reached its limit.
The Transistor Scaling Conundrum
At each technology node, device manufacturers can reduce device area, cost and power consumption and achieve performance improvements by shrinking transistors, also known as PPAC (power, performance, area, cost) scaling. However, further reducing the size of FinFETs limits drive current and electrostatic control capabilities.
In planar transistors, the channel width can be increased to drive more current and increase turn-on and turn-off speeds. However, with the development of CMOS design, the track height of standard cells is continuously reduced, which leads to the limitation of the size of the “fin”, and the single-fin device based on the sub-5nm node will not provide enough drive current.
Furthermore, while all three sides of the “fin” are controlled by the gate, one side is left uncontrolled. As the gate length decreases, the short-channel effect becomes more pronounced and more current leaks through the contactless part of the bottom of the device. As a result, smaller size devices cannot meet power and performance requirements.
Replacing fins with nanosheets
Gate all around (GAA) is a modified transistor structure in which all sides of the channel are in contact with the gate, allowing continuous scaling. Transistors using this structure are known as gate-all-around (GAA) transistors, and many variants of this type of transistor have already appeared.
Early GAA devices used a method of stacking nanosheets vertically, placing horizontal sheets separated from each other into the gate. Compared to FinFETs, the channels under this method are easier to control. And unlike FinFETs, which have to have multiple fins side-by-side to boost current, GAA transistors can achieve higher current-carrying capabilities by simply stacking a few more nanosheets vertically and having the gate wrap the channel. In this way, it is only necessary to scale these nanoflakes to tune the transistor dimensions to meet specific performance requirements.
However, like fins, as technology advances and feature sizes continue to decrease, the width and spacing of fins continues to shrink. When the flakes are nearly equal in width and thickness, these nanoflakes look more like “nanowires.”
Although the concept of nanoflakes is simple, it presents a number of new challenges for practical fabrication, some of which stem from structural fabrication and others related to new materials needed to meet PPAC scaling goals.
Specifically, the main challenge in construction stems from the complexity of the structure. The fabrication of GAA transistors first requires alternating Si and SiGe epitaxial layers to form a superlattice and use it as the basis for the nanoflake structure, and then sinking a dielectric spacer layer inside (for source/drain protection and gate width determination) ) and remove the sacrificial layer of the channel by etching. The space left after removing the sacrificial layer, including the space between the nanosheets, needs to be filled with a gate composed of dielectric and metal. Future gates are likely to use new metal materials, of which cobalt has entered the evaluation stage; ruthenium, molybdenum, nickel and various alloys have also been considered by manufacturers.
GAA transistors will eventually replace FinFETs, and the nanoflakes in them will gradually develop into nanowires. The GAA structure should be able to apply to all advanced process nodes that are currently planned.
Beginning with the earliest planar structures, transistor architectures have come a long way and have effectively driven the development of smart interconnections that were unimaginable by early industry pioneers. With the advent of the all-around gate transistor, we also eagerly expect it to bring even more amazing end-user devices and capabilities to the world.