“In the field of aerospace engineering, long-distance telemetry and remote control such as satellite-to-earth communication is one of the important functions of the embedded satellite digital tube computer. Using the three-wire synchronous serial telemetry and remote control channel to send and receive commands and data is an important part of the communication link.
In the field of aerospace engineering, long-distance telemetry and remote control such as satellite-to-earth communication is one of the important functions of the embedded satellite digital tube computer. Using the three-wire synchronous serial telemetry and remote control channel to send and receive commands and data is an important part of the communication link.
At present, many processor chips have integrated synchronous serial interface, but there are not many processors based on three-wire synchronous serial interface. Although the three-wire synchronous communication hardware circuit interface realized by the traditional design method can meet the general engineering design requirements, driven by the design concept of “low cost, small size, low power consumption and flexibility”, the traditional design obviously does more harm than good . Using programmable logic device CPLD/FPGA technology, the structure design and implementation of the three-wire synchronous serial communication interface circuit can greatly reduce the system volume, reduce power consumption, and improve design flexibility. At the same time, other logic function modules can also be added therein, and can be easily applied to related embedded systems.
1 Three-wire synchronous serial communication mechanism
In three-wire synchronous serial communication, the transmitter and receiver must use a common clock source to maintain accurate synchronization between them. In order to achieve the purpose of accurate synchronization, one of the methods is to use the principle of encoding and decoding, that is, using the encoder at the transmitting end to combine the data to be sent and the transmitting clock, send it to the receiving end through the transmission line, and then use the decoding at the receiving end. The receiver separates the receive clock from the data stream. Commonly used codecs are Manchester codec and NRZ-L code. The code type used in this paper to send and receive signals is the NRZ-L code.
The three-wire synchronous serial communication mainly includes three signals: sampling signal (also called frame synchronization signal), clock signal and serial data signal.
It can be seen from Figure 1 that when data is received or sent, the frame synchronization signal first triggers an instantaneous start pulse, and then remains active low, followed by the clock signal, the data remains stable on the rising edge of the clock signal, and starts Sampling and transmission, one bit of character data is sent and received per clock cycle, and serial data is continuously sent and received in batches.
2 Interface structure design of three-wire synchronous serial communication controller
2.1 Realization of hardware circuit interface based on traditional design
In the traditional hardware circuit design of the three-wire synchronous serial communication controller interface, multiple components are required to realize its functions, including: asynchronous four-bit counter, shift register, 8-bit D flip-flop, AND gate, NAND The main functional devices such as gates and inverters, and the interface circuit schematics are implemented in ProteI 99 SE.
The hardware circuit of the receiving interface of the three-wire synchronous serial communication controller is shown in Figure 2.
It can be seen from FIG. 2 that the logic control function is realized through different combinations of the reset signal rst n, the chip selection signal CS, the gate control signal strobe, and the read and write signal RW. Through the counting function of the asynchronous four-bit counter SN54HC161, the shift register SN54HC164 can smoothly perform the serial/parallel conversion of the data, and the 8-bit parallel data is latched on the internal bus through the 8-bit D flip-flop SN54HC374 to wait for the system to receive. At the output end, the interrupt signal int is generated through the double D flip-flop SN54HC74, which informs the microprocessor in the system to receive data.
The hardware circuit of the sending interface of the three-wire synchronous serial communication controller is shown in Figure 3.
It can be seen from FIG. 3 that the system clock start-clk generates the original signal code-clk of the transmission clock through the frequency dividing circuit module, which is used for the clock state control of the circuit. The microprocessor in the system will pass the 8-bit parallel data to be sent through the 8-bit D flip-flop SN54HC377, and latch the data in its Q port to wait for transmission. parallel/serial conversion operation. At the output end, the interrupt signal is generated through the double D flip-flop SN54HC74, and then the frame synchronization signal, clock signal and data transmission operation is started through the one-way bus driver SN54HC244.
2.2 Interface structure design based on CPLD/FPGA
In order to solve the shortcomings of traditional hardware circuit with many components, high power consumption and large size, it has become a necessity to use CPLD/FPGA technology and VHDL hardware description language to design three-wire synchronous serial communication controller interface. serial communication mechanism,
The internal structure of the three-wire synchronous serial communication controller interface based on CPLD/FPGA is designed, and its functional structure is shown in Figure 4.
The internal structure of the entire three-wire synchronous serial communication controller interface is mainly composed of four modules: clock frequency division module, system interface control logic, data receiving module, and data sending module.
The clock frequency division module is mainly used for the data receiving/transmitting module to generate the synchronous clock signal. The system interface control logic is mainly used for the control of various logic function signals, and can also receive interrupt signals generated by the _interrupt arbitration logic module to control data reception or transmission operations. The data receiving module is the part of the three-wire synchronous serial communication controller interface for data receiving, and its module structure is shown in Figure 5.
Data receiving process: Triggered by the frame synchronization pulse signal, the serial data remains stable when the rising edge of the clock signal rclk arrives, and enters the data receiving module through the rdata signal line. Inside the module, the serial data is converted from serial to parallel, the receiving FIFO is used as a data buffer, and the received data is latched in two address registers specified by the VHDL program. One address unit stores the upper eight bits of the data, and the other one The address unit stores the lower eight bits of the data. When the data is full of these two address units, the interface sends a “receive buffer full” receive interrupt flag int to the system. After the system microprocessor responds, the data is all taken out, and the parallel data It is sent to the data bus of the system, and the same operation is repeated until all data are received continuously, and the data receiving process ends.
The data transmission module is also the part of the three-wire synchronous serial communication interface for data transmission, and its module structure is shown in Figure 6.
Data transmission process: Triggered by the sgate frame synchronization pulse signal, the parallel data on the system data bus remains stable when the rising edge of the clock signal sclk arrives, and data transmission starts through the data transmission module. Inside the module, the FIFO data buffer is first sent. When the parallel data is full of the buffer unit, the data sending module sends a “send buffer full” sending interrupt flag int to the system. After the system microprocessor responds, the parallel data is sent from the sending Read out from the FIFO, convert it into serial data after parallel/serial conversion, before the high-order MSB and after the low-order LSB, and send it to the sending data signal line Sdata, and send it to the peripheral device interface, repeat the same operation until all data is sent. , the data sending process ends.
Based on the introduction of the three-wire synchronous serial communication mechanism, this paper first designs the hardware circuit of the three-wire synchronous serial communication interface. The interface structure of the communication controller describes each functional module and its working principle in detail. The design is reasonable and meets the requirements of practical applications. At present, this interface structure module has been successfully applied to an aerospace project and its supporting hardware test platform as a key sub-module in FPGA design.